how to select io pad in asic design

[floatgrass]

I design my asic.
who can give me some advice about selecting io pad?
welcome any doc about this topic.
thanks!

 

[Monkey]

There are should be design guide from your silicon fab and packaging fab.

It depends on packageing type, core bound or io bound type of design, timing, power and noise considerations.
If your design is io bound, you may choose staggered io cell, which is taller and more slim.
Depending on sytem requirements, you need choose the right power supply voltage.
You need consider SSO, add enough power cells at the right place.
According to timing, choose the driver with proper strogth and slew rate, should be with enough margin but not too much.

 

[power-twq]

some advice on selecting IO pads:

1) current.

2) delay;

3) area;

4) unidirection or birdirection

I design my asic.
who can give me some advice about selecting io pad?
welcome any doc about this topic.
thanks!

 

[arunragavan]

first u must consider the package technologies before going to i/o pad insertion.

 

[gaonkc]

1) current
2) slow rate
3) driver
4) pad bounding? etc

 

[jjww110]

some advice on selecting IO pads:

1) current.

2) delay;

3) noise;

4) unidirection or birdirection

 

[wkong_zhu]

1) drive stength
2) slew rate
3) pull-up/pull-down resistor
4) area