how to see signals details in modelsim main using script?

[LatDrIvE]

Hello all,

I am running a design in modelsim and i would like some of these signals somehow to be displayed as the following :

<At T=159 ns dat a_in <= "0000">

in the modelsim main window and if i can grab these results and write them simultaniously in a TXt file.

thank you

 

[avimit]

Re: how to see signals details in modelsim main using scrip

Hi,
what are you using? vhdl or verilog? you can do what you have asked but you will have to writa a corresponding code. example:

//Display the value of 'data_out' everytime 'success' is received
always @ (posedge load_op_reg)
begin
  $display("Time = %0d : op_reg[8:1] = %d", $time,mem[xbytecounter]);
end

To see the full verilog file from where it is taken see:
http://www.vlsiip.com/verilog/rx_tb.v
If you are using vhdl let me know and I wil tell you how to do it. In vhdl its simpler to dump these things directly into a txt file(than to disply it on modelsim), which wont be visible on modelsim window.
Kr,
Avi
http://www.vlsiip.com

 

[LatDrIvE]

Re: how to see signals details in modelsim main using scrip

thanx Avi
I am using VHDL except a little part in verilog. But the signal want to trace are in VHDL part.

 

[avimit]

Re: how to see signals details in modelsim main using scrip

Hi,
If you are using vhdl its easier to dump your variables into a file directly. You will have to write a code. Here is an example of a vhdl file which writes txt files while simulation is running.
http://www.vlsiip.com/vhdl/fileio.vhd
Look for the process called write_file_p in the above vhdl file. And DO NOT forget to include std.textio.all and use ieee.std_logic_textio.ALL as is present in the above vhdl file
Hope it helps,
Kr,
Avi
http://www.vlsiip.com