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How to see Seed Value in System Verilog

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spartanthewarrior

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Hi All,

How can i see Seed Value in VMM Environment when using System Verilog.
 

spartanthewarrior said:
Hi All,

How can i see Seed Value in VMM Environment when using System Verilog.
Click to expand...

VCS usually prints it to log file I thought (though not 100% sure). Recently it added a system task to get the seed, something like: $get_initial_random_seed() - please check with doc/VCS support. Or if needed I can confirm next week after trying a quick example

Ajeetha, CVC
www.noveldv.com
 

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