Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to run wgl pattern generate by DFT tools,

Status
Not open for further replies.

stormwolf

Advanced Member level 4
Joined
Jan 3, 2004
Messages
112
Helped
12
Reputation
24
Reaction score
0
Trophy points
1,296
Activity points
777
wgl pattern

After ATPG , DFT tools will generate some format pattern , and we generate WGL format pattern , before we just use the testbench generat by ATPG tools ,
now we heard someone use WGL or some other format pattern to run , and i
want to know which tools can do this or how to deal with it . Thanks.
 

WGL files are normally used for the tester (ATE). Most vector translation tools (TSSI, VTRAN) will take WGL as input, and can translate to whatever ATE format you use.

John
DFT Digest
 
Use vtran to convert your wgl files to 1's and 0's.
Vtran also can generate the verilog testbench to run the test
Setup frequency and input output timings in the vtran setup.

Running the verilog test bench generated by vtran will give a pass/fail message at every cycle of the stimulus.

Naveen
Visit http://vlsiforum.com
 

hi ,

If,You can load the design and wgl file into the tool and every tool will genrate the verilog files from the wgl file if you follow this procedure.

regards,
ramesh.s
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top