nemolee
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In my RTL design, I insert gate cell (ex: BUF, AND, MUX) for some consideration.
But I don't want to run RTL simulation with cell delay.
How should I do ?
Thank you.
- - - Updated - - -
I know how to run simulation without cell delay.
Just need to apply +nospecify to run simulation.
But I don't want to run RTL simulation with cell delay.
How should I do ?
Thank you.
- - - Updated - - -
I know how to run simulation without cell delay.
Just need to apply +nospecify to run simulation.
