How to run LVS with out calibre's v2lvs

[hypnustang]

Hi,

I am designing a mixed signal circuit, while for the digital part I could run LVS directly using .v file from encounter with the standard cell cdl file, but for a mixed signal circuit, and I don't have the nettran from synopsys and v2lvs from calibre, we have only assura to run everything, how could I run the LVS......please give me some tips, please...

Thank you really much!
Bison

 

[beeflobill]

The problem is that the Verilog netlist doesn't have all the information required to do LVS. It doesn't have power and ground connections. (You can get those in the netlist, but lets save that for later)

The next problem is that it is unlikely that assura will eat Verilog. What you must do is find out what assura wants as input, and convert the Verilog to that while putting in the power and ground info in the mean time. I'm going to guess here that the format is CDL.

I can think of two approaches to convert the Verilog netlist:
1) Write a script that changes it into whatever format you want. This approach is harder than it sounds, but doable if you are willing to spend a few weeks on it. The challenge is that you must cross reference the cell library used (or which you built just for this) to get the pin ordering and naming correct.

2) Read the Verilog into the tool you are doing your mixed-signal design in. Hook it up, and then export it (or the whole design) in whatever format is required for LVS. Your mixed-signal design tool should already be setup to use the libraries you are using. (If not, then you are screwed for about a month to get all that worked out, but you will have learned a ton by the end of the exercise!) If everything goes smoothly, it should take about a day to figure this out the first time.

I recommend the second approach unless you can't do it for whatever reason. This way you have a greater change of having confidence that you've integrated the digital and analog correctly in design and for LVS.

 

[hypnustang]

Hi beeflobill,

Thank you sooo much for your reply, finally I fixed this problem, I found a way to run LVS without translate the .v to .cdl since Assura could read .v directly, just need to change some parts in the digital part's netlist, and the standard cell cdl file, also in the cdl file of the whole circuit.

I will try to write a tutorial for this when I am available, so busy right now, and hope that would help others.

Thank you very much again,
Bison