Hi guys, recently I tried to design a CML latch, do an AC analysis of CML latch is necessary? 1. No matter with or without inductor peaking, how to run the AC analysis?
2. Could common mode and swing of the data input and clock input the same?
Thank you.
I have read a lot of material, but I still don't know how to decide the variable and doing the simulation, I am using 45nm with 0.9 VDD.
You would run the logic string (not a single gate; you
need to optimize in context of normal input swing (so
buffer the front by a couple of layers) and output load
(so at least one and probably N=fanoutMax gates hung
on the back)) with a couple of different pulse trains
(like max clock freq, and min transition-density - an
inductor-peaked output is probably not good for static
logic) and look at the family of output pulse shapes
across the sensible range of inductor values. These
will be limited by how much chip area you want to
allocate (inductors are one of the chubbiest layout
elements) and what edge-rate / frequency you are
expecting to work at.
Pick the one that gives highest amplitude without any
duty cycle distortion. Eyeball will do. Then repeat at
corners (PVT) over a lesser grind-range to find the
sweet spot.