[SOLVED] How to Reset the D flip flop in the following code?

[dragonfury]

How can I get a reset input and reset the D-flip flop in the following code ? Your kind help would be appreciated as I have no knowledge of Verilog

module d_ff(vin_d, vclk, vout_q, vout_qbar);
input vclk, vin_d;
output vout_q, vout_qbar;
electrical vout_q, vout_qbar, vclk, vin_d;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

integer x;

analog begin
@ (cross( V(vclk) - vtrans_clk, +1 ))
x = (V(vin_d) > vtrans);
V(vout_q) <+ transition( vlogic_high*x + vlogic_low*!x, tdel, trise, tfall );
V(vout_qbar) <+ transition( vlogic_high*!x + vlogic_low*x, tdel, trise, tfall );

end

endmodule

 

[FvM]

I have no knowledge of Verilog

The shown code uses Verilog-A rather than standard Verilog syntax and isn't related to digital logic design in my opinion.

My first suggestion would be to find out, what's the reason of using Verilog-A to describe a simple FF. And if it serves a purpose, learn the respective syntax.

 

[dragonfury]

The shown code uses Verilog-A rather than standard Verilog syntax and isn't related to digital logic design in my opinion.

My first suggestion would be to find out, what's the reason of using Verilog-A to describe a simple FF. And if it serves a purpose, learn the respective syntax.

The editor /compiler for this code supports verilog-A (using cadence virtuoso). I have found a lot of codes/tutorials for standard verilog but none to explain me Verilog-A :-?

 

[FvM]

Verilog-A is mostly used for mixed-signal circuit simulation, that's why I asked for your intentions. You should be able to find some Verilog-A tool and reference manuals on the internet, e.g. the "Verilog-A Reference Manual". But I don't think, that's it's of much use without learning the basic "digital" Verilog language before.

 

[dragonfury]

Verilog A is only for analog. Verilog AMS is for mixed signals.

 

[FvM]

Verilog A is only for analog. Verilog AMS is for mixed signals.

I see you're starting to learn. Nevertheless can Verilog-A be used for mixed-signal simulation. Which is obvious by the fact, that Verilog-A still supports the full basic Verilog language syntax.

 

[dragonfury]

i guess so. but would you kind help me with the code ?

 

[FvM]

I can tell you the standard Verilog syntax for a FF with (ansynchronous) reset, you have to translate it to respective Verilog-A constructs.

always @(posedge vclk or posedge vreset)
begin
  if (vreset = 1)
    begin
      vout_q = 0;
      vout_qbar = 1;
    end
  else
    begin
      vout_q = vin_d;
      vout_qbar = ~vin_d;
    end
end