How to represent a floating point number using reg variable

[muni123]

Hi,
How can we design a divider so that the we can preseve the value after decimal point in verilog HDL
Ex: If we need to divide the 3'b100 by 2 we will do it by right shifting 3'b100 by 1 time.
if we need to divide 3'b100 by 8 we will do it by right shifting 3'b100 by 3 times. But we cant preserve the value after the decimal pont ie., 0.1 in Verilog if we took a reg variable.

How can we implement it in verilog.

Thanks in adavance!!

 

[sudhirkv]

Re: How to represent a floating point number using reg varia

If you want to preserve the decimal value you have to use floating point divider. This core is available in opencores.