How to replicate this VHDL process in Verilog ?

[dcreddy1980]

VHDL to Verilog

Hi,

Can any body suggest, how we can replicate the below process in to verilog behavioral model :

process(A,B,C,D)
begin
if((A'event and A = '1') or (B'event and B = '1')) then
tmp <= '1';
elsif((C'event and C = '1') or (D'event and D = '1')) then
tmp <= '0';
end if;
end process;

Regards,
dcreddy

 

[Shurik]

Re: VHDL to Verilog

I think will be so:

always @( posedge A or posedge B or posedge C or posedge D)
if (C )
tmp<=1'b0;
else
if (D)
tmp<=1'b0;
else
if (A | B)
tmp<=1'b1;

 

[jjww110]

VHDL to Verilog

I think will be so:

always @( A or B or C or D)
if (A | B )
tmp<=1'b0;
else
if (C | D)
tmp<=1'b0;

 

[dcreddy1980]

Re: VHDL to Verilog

always @( A or B or C or D)
if (A | B )
tmp<=1'b0;
else
if (C | D)
tmp<=1'b0

Does this really represent the below process?

process(A,B,C,D)
begin
if((A'event and A = '1') or (B'event and B = '1')) then
tmp <= '1';
elsif((C'event and C = '1') or (D'event and D = '1')) then
tmp <= '0';
end if;
end process;

 

[Dr_MS]

VHDL to Verilog

always (posedge a or posedge b or posedge c or posedge d)
if (a || b)
tmp<=1'b0;
else
tmp<=1'b1;

 

[jameshou082705]

Re: VHDL to Verilog

It depends.

If a, b, c, d are clock signals, we can implememt it as a
sequential logic as the following:

always @(postedge a or postedge b or postedge c or postedge d)
begin
if (a||b)
tmp = 1'b0;
else
tmp = 1b'1;
end

Otherwisw, we should implement it as
combinational logic as the following:

always@ (a or b or c or d)
begin

if (a || b)
tmp = 1b'0;
alse
tmp = 1b'1;
end

 

[shiv_emf]

VHDL to Verilog

which is correct? :O