How to remove negative slack in a path after running timing optimization?

[p_shinde]

hi,

when we have negative slack in a path , while using soc encounter, we to timing optimization to remove it, rgt?

but if after running timing optimization for several iterations then also negative slacks dont disappear then what to do?

reply soon,

thanks,

 

[funzero]

how to fix negative slack

repartition some big block such as memory cpu , and to p&r again.

 

[p_shinde]

Re: negative slack

hi,

is that the only solution to run PnR again?

thanks,
Prasad

 

[spauls]

Re: negative slack

Please see timing path very carefully , there may be high fanout cells in your design, try to optimize specific areas.

 

[nav_vlsi]

Re: negative slack

mostly cells with lower drive strength cause these problem , if possible hide these cells before( if those cells are critical for your design , then dont touch them) P&R. also try to size those cells which have high fanout. and u can do regioning or grouping of cells

 

[p_shinde]

Re: negative slack

resize a cell, then we have to resize a complete row for that...?

also want to know how do we read a slack file from slack browser, as when we click on a -ve slack net, we get the logic ckt for that net....

then what to do???????????


also after clicking on a net, we get another window of nets (guess thats internal nets betwn those points causing -ve slack), then what to do looking at it..?

thanks,
Prasad

 

[zhangpengyu]

negative slack

using pipleline

 

[kapil_vlsi]

Re: negative slack

Hi,

negative slack are different types : set up slack and hold slack. u can negative slack in setup and hold also. So, one way correcting hold violations is inserting delay cells in clock tree synthesis. Also, setup violations can we corrected by sizing the cells and declaring multicycle paths if there are two cycles.

Regards,
KAPIL B

 

[manivannanrm]

Re: negative slack

After timing optimization we should get +slack.if negative value is there we should fix it so that setup time violation will not be there.We wont consider hold violation at this stage.(ie before placement)

Only after layout design gets over we think about hold violations ie during CTS.So never care abt hold time violations before placement of cells.