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How to remove assign statement in netlist

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zeese

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synopsys netlist + solvnet

How do I remove assign statement in a synthesized netlist?

I read somewhere on the net, this assign statement exists
because
1) Input connected directly to output port
2) There is tristate cell

I'm more concern on how to solve the (1) because in my design,
there should not be a tristate cell (unless dc puts it without my notice).

Is there any dc command to prevent assign statement in netlist?
Or any other solution?
Thank you.
 

silencer3

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remove assign dc

in the environment setup or in the dc script, add "set_fix_multiple_port_nets -all -buffer_constants ". this will eliminate assign statement problem.

refer solvnet for complete info. refer the following article,

https://solvnet.synopsys.com/retrieve/003637.html
 

    zeese

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zhustudio

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add
set verilogout_no_tri true
set_fix_multiple_port_nets -all -buffer_constants
before you write out verilog netlist
and add
change_name -hier -rule verilog
to give better naming in netlist

good luck :)
 

    zeese

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Raptor

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I remember reading a document on solvnet which stated that this is a bug in DC 2004.06(or 2004.12). The solution was to read in the netlist and write out again without issuing any command for optimization.

hope this helps.
 

    zeese

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zeese

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I like the solution gave by Raptor. I tried it, and it works.
To me, this is the simplest one. Thank you.

But I hope someone can help me find the articles in solvnet.
I'm also still trying to find it.
 

ls000rhb

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to Raptor:
I remember reading a document on solvnet which stated that this is a bug in DC 2004.06(or 2004.12). The solution was to read in the netlist and write out again without issuing any command for optimization.

The netlist to which you referred here is the optimized gate-level netlist?

i want to affim the point!
 

Raptor

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finally found the document:

docid :015123
title : Verilog Netlist Has Assignments to Wires With _snps_wire Suffix in Version W-2004.12
 
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