I have just the same doubt.
How to minimize offset in circuit design and layout?
Could anyone show some general method to improve the offset issue.
Thx in advance.
The offset of a comparator can be distinguished as systematic offset and random offset. Systematic offset can be elimated, but random offset can't. The main reason of offset is process mismatch.
Of course you can increase transistor size to reduce mismatch, but the speed issue shoud be considered.
Razavi's AIC book reveals many method to deal with offset cancellation, for example, IOS,OOS,etc.
From schematic, If possible, use larger size transistor, pay attention to the bias current ratio between first and second stage.
From layout, unit matching, common-centroid, dummy devices, the same current direction in the matching pairs would be better.
choping uses switch transistors. But chopping usually need a large RC filter to get rid of the ripple. It's not too practically in many application.
offset of input pair is inverse proportional to the sqrt(L*W) of input transistors. So larger device makes smaller offset. Speed/power may suffer if the size is too big.
one way to get around is use some calibration. add some trim around input.
surely making devices bigger will reduce your offset, but you should also pay more power if you want to maintain other parameters like Gain and GBW the same.
Other than scaling, some circuit techniques can be used to reduce the offset of the opamp. These include autozeroing (AZ), which is a sampling technique, and correlated double sampling (CDS), which is a particular case of AZ and chopper stabilization (CHS) which is a modulation technique and can be used in continuous time system.