How to reduce the delay of 8 bit adder?

[zitty]

hey all,

i´m quite a beginner in digital design and i´d need some help with some system considerations. i work with a 100nm cmos process. and 1GHz sampling frequency

in my system i get the data out of 2 clocked registers which have 7 bit length.
i want to add the data of these registers with a digital adder.

as far as i know i need a register at the output of the adder so that the data is stored there.
but then this register will also be clocked and cause an additional delay.

am i right with the assumtion that without the register at the output data will not be stable?
the output data will be fed back into another system so that stable data during one clock cycle are required.
is there another possibility of adding without requireing an additional register?

how can i reduce the delay of this addition?

thanks all.

 

[aquakeerthi]

y dont u show your coding then it would be better to solve easily

 

[qieda]

Hi,

I think doing a 7bit + 7bit adding within one clock cycle @ 1GHz (means 1ns cycle time) is not possible.
If I understand you correct you even want to use the result in the same clock cycle.

You need to have a pipelined architecture

regards

 

[zitty]

hey,

aquakeerthi:
at the moment this are just general considerations. i´m only working on rtl level. so i dont have any code.

qieda:
exactly i want to use the results in the same clock cycle. I measured a gate delay of 11ps of a normal cmos inverter.
would it be possible if i´m only using a 5 or 6 bit addition?
maybe i could reduce the wordlength. what kind of key words should i look for?

 

[lostinxlation]

The simplest way is splitting it to the upper 4 bit addition and lower 4 bit addition. THe lower 4 bits are simply added. Upper 4 bits have 2 sets of adder, one has 0 as an carry in, another has 1 as an carry-in. and the result from one of those 2 adders are selected by carry-out from lower 4 bits. THe critical path should be roughly with 10 levels of logic.
There are many addition algorithms, but having only 8 bits, i don't think they make much difference in speed. I guess carry select adder like above should be enough.

 

[qieda]

Hi

exactly i want to use the results in the same clock cycle. I measured a gate delay of 11ps of a normal cmos inverter.

your technology is quite fast. I'm using 65nm here. Looking at the synthesis reports an Invertes is around 25ps in my design. (at worst case corner)

Comming back to your questions

am i right with the assumtion that without the register at the output data will not be stable?

since your input is stable (because it is comming from a register) your output of the adder will also be stable after some time.

the output data will be fed back into another system so that stable data during one clock cycle are required.

what is the requirement of the other system.
How fast does your adder have to be (e.g. 300ps)

i´m only working on rtl level.

Can you do a try synthesis to get first timing results. Normally the synthesis tools take the fastest implementation for the adder.


regards