How to reduce the current mismatch in PFD and CP blocks of a PLL?

frankiebai said:

I designed a Phase-Frequency-Detector and an Charge-Pump, as blocks of a PLL.
And what parameters I should measure of this two blocks?
The mismatch of Iup and Idn and the stability of the CP?
And anymore?

About the current mismatch, what method I should use?
The method I used is to connect a dc voltage source with the CP output, and make dc sweep of this source from 0 to VDD when only Iup and Idn is working, is it right?

Click to expand...

jecyhale said:

frankiebai said:

I designed a Phase-Frequency-Detector and an Charge-Pump, as blocks of a PLL.
And what parameters I should measure of this two blocks?
The mismatch of Iup and Idn and the stability of the CP?
And anymore?

About the current mismatch, what method I should use?
The method I used is to connect a dc voltage source with the CP output, and make dc sweep of this source from 0 to VDD when only Iup and Idn is working, is it right?

Click to expand...

Yes, I use the high swing cascode current mirror as the current source.
It can reduce the current mismatch.
And you should simulate the glith of CP when the switch is on/off.
Besides, you can simulation the highest operation frequency of PFD.

Click to expand...

frankiebai said:

Hi, jecyhale,
Thank you!
Can you tell me how to simulate the glith of CP when switchs on/off?
My reference frequency is 1MHZ, and I use the pulse source with the period is 1us,
the duty cycle is 50%, and the up and dn source have 50ns difference in time domain, the result is that only Iup or Idn is working in the 50ns, Is this method right?

jecyhale said:

frankiebai said:

I designed a Phase-Frequency-Detector and an Charge-Pump, as blocks of a PLL.
And what parameters I should measure of this two blocks?
The mismatch of Iup and Idn and the stability of the CP?
And anymore?

About the current mismatch, what method I should use?
The method I used is to connect a dc voltage source with the CP output, and make dc sweep of this source from 0 to VDD when only Iup and Idn is working, is it right?

Click to expand...

Yes, I use the high swing cascode current mirror as the current source.
It can reduce the current mismatch.
And you should simulate the glith of CP when the switch is on/off.
Besides, you can simulation the highest operation frequency of PFD.

Click to expand...

Click to expand...

frankiebai said:

Hi, jecyhale,
Thank you!
Can you tell me how to simulate the glith of CP when switchs on/off?
My reference frequency is 1MHZ, and I use the pulse source with the period is 1us,
the duty cycle is 50%, and the up and dn source have 50ns difference in time domain, the result is that only Iup or Idn is working in the 50ns, Is this method right?

jecyhale said:

frankiebai said:

I designed a Phase-Frequency-Detector and an Charge-Pump, as blocks of a PLL.
And what parameters I should measure of this two blocks?
The mismatch of Iup and Idn and the stability of the CP?
And anymore?

About the current mismatch, what method I should use?
The method I used is to connect a dc voltage source with the CP output, and make dc sweep of this source from 0 to VDD when only Iup and Idn is working, is it right?

Click to expand...

Yes, I use the high swing cascode current mirror as the current source.
It can reduce the current mismatch.
And you should simulate the glith of CP when the switch is on/off.
Besides, you can simulation the highest operation frequency of PFD.

Click to expand...

Click to expand...