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How to reduce power in back-end flow?

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blueant

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I'm a back-end engineer. Anyone can tell me how to reduce power in back-end flow? And some tools?
Thanks.
 

sree205

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i don't know much about tool perspective, but, recently, we have a concept called power-gating very much akin to clock gating. concepts called multi-vdd and multi-Vt are also used to reduce power consumption. to get a better idea, read "low power design methodologies" by jan rabaey.
 

blueant

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Thank you sree205.
But clock-gating and multi-Vt should be done by front-end engineer, what can back-end designer do?

In addition, I not found the book, pls help me, thanks
 

eternal_nan

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You are wrong on both counts. Both clock gating and Vt swapping are usually at least improved upon in the back end (post synthesis). In fact, most companies do Vt swaps on post-layout netlists since the timing is more accurate.

Beyond this, back end designers can attempt to route signals that belong to fast clock domains on metal layer with lower cap / um of minimum width wire. They can try to space out fast switching signals with more than minimum spacing. Improve flloor plans to reduce long routes.
 

bbgil

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hi. this may sound silly, but can you described back-end flow and its difference with front-end flow, if there is such a term. thank you
 

srkumar81

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u can do multi VDD as well as power gating. U can also use power switches to minimize the power consumption.
 

blueant

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I think multi-vdd should use difference voltage libraries to synthesis, right?
Anyone can tell me how do it detailly? Or intraduce some papers.
Thanks.
 

sumit_techkgp

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The biggest problem back end operations and so much constrained by design constraints and system deign, practically power reduction is not possible in back end operations. In Layout also, sloppy layout can increase current consumption but good layout cannot decrease power!!!!!!
 

srkumar81

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For multi-vdd u can use different libraries for synthesis. The layout itself is divided into several voltage domains. When a cell from low-voltage domain speaks with cell in high-voltage domain, then you have to use level shifters for that.
 

wkong_zhu

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use power compiler can help.
It use clock gating method, but give you DFT problem in the same time. You can balance.
 

lnc

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There are many methods and technologies to reduce the total power consumption on a chip design.
In general, the total power consumption is sum of two components:
1. Static power consumption ( Standby power)
It is known as leakage power.
2. Dynamic power ( Active power)
2.1 Discharging/Charging external cap. (SWCAP power)
2.2 Internal power.
 

shiv_emf

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power islands or power domain swtiching ..
clock gating, multi voltage domain ..these r few low power design techniques but HOW r thry implemented????????????
is it front end or back end job...?
I think front end synthesis will hav different libraries for each voltage domain .... correct me if i'm wrong
thanks
Shiv
 

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