I am designing a VCO using the voltage-to-current converter as shown in the Fig.13 of "A PLL Clock generator with 5 to 110MHz of lock range for microprocessors" JSSC. 1992 Nov.
Phase noise simulation(PSS, Pnoise) results shows the main noise source is the voltage-to-current converter NMOS and PMOS(drain-source resistance thermal noise).
To reduce the phase noise, either you increase the quality factor of the coils used ,or you can increase the output power .Increasing the output voltage by factor of N invreases he carrier power by N^2 while the noise power increases by N leading to better noise performance .
You can refer to "RF Microelectronics" by Razavi for more information chapter 7 pages from 220 to 225 .