I am trying to implement an AM demodulator on ZYNQ 706 FPGA. To ensure the quality of output I need a higher Fixed Data type. this required a large number of DSP slices. Is there any method to reduce the number of DSP slices without reducing the DATA TYPE
If the sampling frequency is considerably lower than core clock, you might think about using serial multipliers, no ready-to-use IP available unfortunately.
In multi-channel design with many channels, a sequential (muxed) usage of demodulator blocks can be considered.
However, a recent FPGA should have sufficient DSP resources to implement a moderate amount of channels fully parallel.
If the sampling frequency is considerably lower than core clock, you might think about using serial multipliers, no ready-to-use IP available unfortunately.
In multi-channel design with many channels, a sequential (muxed) usage of demodulator blocks can be considered.
However, a recent FPGA should have sufficient DSP resources to implement a moderate amount of channels fully parallel.
I have programmable FIR filters in my design that are consuming DSP resources what should be done in this aspect keeping in view I cant reduce data type and filter order