How to reduce buffers in number and area?

[apradeep]

Hi all
I was doing cts for one of the clock trees in the design
I want to control the max no of buffers to 50 (presntly tool had put 100 buffers)
can u suggest me the possible way
i have tried by constraining transition time and phase delay (skew is given as 500ps which is required)
Thanks & Regards
Pradeep

 

[anjali]

Re: cts socencounter

Actually tool inserts buffers in clock tree to reduce the clock skew. adding buffers results less delays in the clock network, intern reduces the clock skew.

Then why do you want to reduce the number of buffers? to reduce area! for that we need to concentrate on the logic area.

 

[apradeep]

Re: cts socencounter

Hi anjali
Yes what i what to get by reducing buffers is area(to reduce conjection) as well as power
You had mentioned that by inserting buffers we can decrease delay in clock network can u elobrate it can i get any material regarding that
I think it to reduce reduce skew by making insertion delay same to all leaf pins
Thanks