how to recover the clock in digital communication.what are the best way to do this

[tulsi]

How to recover the clock from serial data(serial data coming from Rz encoder) to get original data in digital communication.
What are the different methods to do this. Please help me.

Thanks in advance

 

[chuckey]

One possible way would be to generate a local clock, which is phase locked to the incoming signal, the trouble is that if a long string of '0's are sent, the clock will drift out of synchronism. Another way would be to just generate an accurate clock, hope the transmission clock is stable and let it run, with perhaps a clock phase reversal after synchronism has been lost for 5 seconds?
Frank

 

[FvM]

As an additional remark, reliable protocols with clock recovery are using data codings with a guaranteed minium number of signal transitions. This can be achieved with bit stuffing (USB, synchronous PPP) or special encoding (manchester, 8B/10B).

 

[tulsi]

As an additional remark, reliable protocols with clock recovery are using data codings with a guaranteed minium number of signal transitions. This can be achieved with bit stuffing (USB, synchronous PPP) or special encoding (manchester, 8B/10B).

hi,
how to do with 8B/10 B encoding ,can you explain little detail,
and can we recover clock and data by edge detection( xor with delay).

 

[FvM]

8B/10B encoding has other properties that make it (or similar methods) a preferred choice for many communication standards, particularly DC balancing and embedded sync detection. See a brief description at Wikipedia and the original IBM patent describing it:
https://en.wikipedia.org/wiki/8B10B
https://www.edaboard.com/threads/241932/#post1035239

Generally, you need a kind of PLL or DLL to track the recovered clock. For each input data edge, you'll check the deviation from expected transition time and feed the error to the PLL/DLL controller. The input data is then sampled in the middle of the data window.

 

[tulsi]

8B/10B encoding has other properties that make it (or similar methods) a preferred choice for many communication standards, particularly DC balancing and embedded sync detection. See a brief description at Wikipedia and the original IBM patent describing it:
https://en.wikipedia.org/wiki/8B10B
https://www.edaboard.com/threads/241932/#post1035239

Generally, you need a kind of PLL or DLL to track the recovered clock. For each input data edge, you'll check the deviation from expected transition time and feed the error to the PLL/DLL controller. The input data is then sampled in the middle of the data window.

i would like to thanks for your quick reply.
even i suggested my madam to use pll but she said how u implement pll in digital communication as it is an analog pll .Is any other simple method to recover clock at the receiver in digital communication which can be implement on fpga.

 

[FvM]

The available clock recovery methods (often designated CDR, clock and data recovery) depend on the data rate. For low and medium data rates, oversampling methods are often suitable.

A basic analog PLL doesn't work for it, you need a least a special phase detector to hold the PLL loop signal when no input edges are present. A popular method locks an analog PLL to a reference oscillator and selects one of multiple phase shifted VCO outputs as recovered clock. Presuming a constant reference and thus constant VCO frequency, the CDR unit implements a DLL rather than PLL.

 

[tulsi]

The available clock recovery methods (often designated CDR, clock and data recovery) depend on the data rate. For low and medium data rates, oversampling methods are often suitable.

A basic analog PLL doesn't work for it, you need a least a special phase detector to hold the PLL loop signal when no input edges are present. A popular method locks an analog PLL to a reference oscillator and selects one of multiple phase shifted VCO outputs as recovered clock. Presuming a constant reference and thus constant VCO frequency, the CDR unit implements a DLL rather than PLL.

thanks for your positive responses towards my threads.
what are the different mechanism for clock recovery.can we use BER method.
how to synchronise data and recover data at the receiver.
which decoding technique is useful in digital communication,which can be implemt on fpga .

 

[FvM]

Many questions. I would ask for the data rate first to discuss suitable implementation methods. BER minimization is of course a criterion for CDR performance, but not particularly an applicable method to design a CDR, I assume.

 

[tulsi]

Many questions. I would ask for the data rate first to discuss suitable implementation methods. BER minimization is of course a criterion for CDR performance, but not particularly an applicable method to design a CDR, I assume.

for low speed 12kbps and for hi speed 100k bit per sec.

 

[FvM]

for low speed 12kbps and for hi speed 100k bit per sec

That's pretty low and can be achieved with different kinds of all-digital PLLs. Different from an analog PLL, the recovered clock is time discrete, according to the system clock edges.

 

[tulsi]

That's pretty low and can be achieved with different kinds of all-digital PLLs. Different from an analog PLL, the recovered clock is time discrete, according to the system clock edges.

thank you..
im using dpll and it contains edge detection and sampling method right.
is there any vhdl code for clock recovery bec im new to vhdl and im finding lot difficulties in understatnding it.
atleast give me logic.
you can mail me at tulsi8788@gmail.com
Thanks in advance

 

[FvM]

I have seen ADPLL codes implementing a design from Best's PLL book. It has been discussed some time ago at Alteraforum. But I never used it and the guy working with the code had some problems. I would probably implement an all-digital PLL from the scratch if I need it.