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how to realize linearity tuning DCXO?

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pigkiller

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Any good idea to realize linearity tuning DCXO? It means frequency is monotonicity when control bits from minimum to maximum.

traditional switch capbank like we use in VCO is hard to achieve linearity tuning when using more tuning bits (12bits~14bits), bits from 011111111111 to 100000000000, it always turned to be nonlinear due to parasitics.

Any good idea for this? What do you think about this?
 

rfsystem

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Is the nonlinerity at higher resolutions 12-14bit because of smaller switched caps, or because you try to use switched C2C-ladders instead of parallel switched caps?

Do you use MOS-varactor caps where the bulk or gate voltage is switched or do you use MOS-switched MiM-caps?
 

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