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how to realize a SPI interface with VHDL?

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sabres

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spi master interface vhdl

help me, please :cry:

Added after 4 hours 3 minutes:

why I have to syncronize the SPI clock with the FPGA master clock??????
In my opinion it can working the modul drivin' only by the SPI-Master clock??

Any opinion, answer will be appreciated, thanks
 

hcet

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spi core vhdl

Maybe this will help you
**broken link removed**

ep20k
 

FvM

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vhdl code for spi_access

Hello,

I can give you an principle SPI slave example. The shiftregister is operated from SPI clock. That isn't generally necessary, but gives a wider range of SPI clock speed in relation to FPGA/CPLD clock. As a disadvantage, synchronisation of data available event is necessary.

Regards,
Frank
 
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bhaskarbhomia

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hi, my project is to interface PIC18F microcontroller with FPGA using SPI interface. the PIC microcontroller will act as a master and FPGA will be slave. can anybody help??? i dont know from where to start???
 

rca

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SPI3 & SPI4.2 is a System Packet Interface, not the same as the simple SPI Serial Port Interface.
 

vishwa

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Hi,

Link: **broken link removed**
This link may help you more in understanding SPI protocol. Check this.

Regards,
Viswa

---------- Post added at 12:23 ---------- Previous post was at 12:21 ----------

Hi,

**broken link removed**

This link may help you more in understanding SPI protocol. Check this.

Regards,
Vishwa
 

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anshu.kad69@gmail.com

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I just found this link **broken link removed**
it contains a sample code for spi interface using FPGA.
 

some_guy

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mayaraj

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Re: spi controller vhdl

can you please send me your version of SPI in vhdl?
thankyou,
maya

- - - Updated - - -

can you please send me vhdl code for SPI ?
thankyou,
maya
at ymq8328:

you still searching a VHDL code of SPI ? If you want send me a private message, I send you my version on SPI (wrote in VHDL).

Regards
Lukee
 

mrflibble

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Re: spi controller vhdl

can you please send me your version of SPI in vhdl?

I see that besides a CIC decimation module you also have SPI on your shopping list. Two points .... First: check out the links provided by some_guy right above your post. And the second more sobering point ... implementing SPI is pretty trivial. Hell, it was one of the first things I wrote when learning verilog. Purely because it was easier than trying to figure out someone elses code back then. It really is easy, just try it. :) And the reason I suggest you try at least implement SPI yourself... If implementing something as easy as SPI is beyond your current skills (no prob, you can always learn), then it would be of no use to give you full working vhdl code for CIC decimation anyways. Why? Because you would have no clue how to integrate it into a working design, that's why. :p

So if you really want to learn VHDL, you might as well try to do the SPI yourself. After that look for useable VHDL for the other items on your shopping list and try and integrate that. Then come to the conclusion that well documented HDL is hard to come by, cave in, and code up the rest of the HDL yourself as well. And voila, you are suddenly well on your way to mastering the HDL of your choice. ;-)
 
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