How to realize a sample rate of 1G/s

[RoboColor]

I saw the advertisement of an oscillograph at the top of this website. It can realize a smple rate of 1G/s. I wonder how to realize it? Is there a AD converter has such high speed? or is there any memory can save the result data in such a high speed?

Who can give me some idea? thanks a lot!

 

[jonw0224]

You can use multiple systems in parallel timed so that they sample in turn. Each ADC can have its own dedicated memory and control but the timing is in concert. Here's an example:

Suppose that you had 2 ADC that each sample at 50 MHz but timed to sample in this order:

ADC1 - Samples a0
ADC2 - Samples a1 (10 ns later)
ADC1 - Samples a2 (10 ns later, but 20 ns after the prior ADC1 sample)
ADC2 - Samples a3 (10 ns later, but 20 ns after the prior ADC2 sample)
etc.

It would be easy to read the memory in such a way as to reconstruct the data (i.e. [a0, a1, a2, a3, ...]). The equivalent sampling would be 100 MHz.

In the case of a repetitive waveform, you can do the same thing with a single ADC sampling at various timings after multiple triggers. The assumption is that the waveform isn't changing so you can sample it differently over multiple periods and represent it as being sampled over one period. Here's an example:

Trigger Event
ADC - Samples a0 (10 ns after trigger)
ADC - Samples a2 (20 ns later, 30 ns after trigger)
...

Next Trigger Event
ADC - Samples a1 (20 ns after trigger)
ADC - Samples a3(20 ns later, 40 ns after trigger)
...

Reconstruct with order [a0, a1, a2, a3...] and the equivalent sampling rate is 100 MHz.

-jonathan

 

[Vacuum]

Hello jonw0224. Thank you for a good explanation.
Do you know the methods how to realize sampling in equivalent time (RIS mode)? I tried to use analog comparator with FPGA (fpga has 1 counter - with 100Mhz clock, 2 counter - with 99.0099Mhz clock) Then, I have difference in edges about 100pS * N (where N- number of clocks). But this scheme seems not adequately work.
Now I try to use PLL in StratixII device. I can reconfigure it on-fly and change phase of clock.
I come to a conclusion that I need a totaly ANALOG synchronization circuit, and ADC also should not clocked from FPGA :-( . What then should I use? Please, help.

 

[echo47]

You can buy 1 Gsps ADCs. Here are a few examples:
**broken link removed**
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You can store 1 gigabyte/sec into slower RAM by simply transferring multiple bytes simultaneously into a wide RAM.

I wonder how Tektronix samples at 50 Gsps, like in these scopes:
**broken link removed**

Maybe helpful, but not much implementation detail:
"Real-Time Versus Equivalent-Time Sampling"
http://www.tek.com/Measurement/cgi-bin/framed.pl?Document=/Measurement/App_Notes/RTvET/ap-RTvET.html

Maybe useful: Some FPGAs have the ability to dynamically adjust the delay of an input or output pin. I've used a Virtex-4 "IDELAY" to generate a pulse edge that gradually moves in increments of about 75ps. The big drawback is the Virtex-4 can't change the delay very quickly.