how to realize a analog delay line

[Luwengao]

Hello,
I want to design a analog delay line. Input signal is voltage source vin (analog signal), the clock freq. is 10MHz, vout is output voltage of the analog delay line, vout(n*T)=vin((n-5)*T).
when t=T (T=100ns), vin(T) is sampled to analog delay line;
when t=2T, vin(2T) is sampled to analog delay line;
when t=3T, vin(3T) is sampled to analog delay line;
……
when t=6T, vin(6T) is sampled to analog delay line, and vout(6T)=vin(T);
when t=7T, vin(7T) is sampled to analog delay line, and vout(7T)=vin(2T);
how to realize this analog delay line using CMOS process.
Thanks a lot.
By the way: very low power dissipation is required for this design!

 

[wued]

you can try shifter registers and analog switches sample?

 

[flatulent]

You have several choices.

ADC-memory-DAC with the memory acting like a FIFO with a rotating pointer.

Charge coupled devices. These were popular in the past but might not be available now.

LC networks emulating a transmission line.

Acoustics in a mercury column. (This was in the past used as a recirculating memory for digital signals. Sort of like a dynamic RAM)