YesI am wondering whether the possibility of readback a specific address (for example 0000,000) from FPGA to the PC?
Good thing you pointed it out, I hadn't noticed. It just looked like a bunch of zeros with a comma.Notice that the first for digits are Frame Address and the rest three digits are the bit address.
UART can be implemented in an FPGA.I think to its possibility via UART interface, but I am not sure about it. Kind helps are cordially appreciated.
Yes, UART would be a simple way.
Remember that you have to send the address serially and then get back the data serially (bigger the h/w register, more will be the time taken).
Even simpler (if you are using Vivado and 7 series or ultrascale parts) is to just instantiate the JTAG-to-AXI4 master. Then all you use are Tcl commands from a Vivado shell to write/read addresses on the AXI bus.
Indeed, I am using ISE 14.7 targeting a Virtex-5 (XC5VLX50T) FPGA, nor the VIVADO. Is it possible to do so with ISE as well? If so, could you please let me know how to do it with JTAG?
Thanks and Regards,
Thanks @dpaul for your kind reply.
A question please: is it possible to share only 1 urart port for sending address from PC to FPGA and also reading back from FPGA to PC at the same time??
I am not familiar with the Virtex-5 (XC5VLX50T) and the development board which contains this part. Also I am using Vivado 2015.4 and it has been years I have not used the ISE suite. So I can only answer your question in a generic way.
Taking the example of the AC701 development board it contains a USB-to-UART Bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS). So I connect my dev board to my PC using the USB cable. Hence I have separate Rx and Tx pins. Using TeraTerm on my PC and a Xilinx UART IP on the dev board, I can easily send and receive signals.
I do this this way only because of my available infrastructure. I am happy with this full-duplex support.
Now in your case you want to use only 1 port for Rx/Tx. While the UART module in your FPGA can be easily modified to use an inout port, I am not sure how this will be handled on the PC side (you have to find this out)!
Secondly sharing only 1 port will enable half-duplex operation. This will slow your communication.
Hope this helps.
Teraterm is an open source terminal program, hyperterminal will work just fine.[/QUOTE]About TeraTerm that you have mentioned, is it a terminal like hyperterminal for Serial communication?? May I use hyperterminal instead?
[/QUOTE]Teraterm is an open source terminal program, hyperterminal will work just fine.
A UART is just a physical interface to transfer bytes, the concept of address and data will have to be a protocol you design on top of the physical UART layer.
It would be whole lot easier to just use some pre-built canned solution from the vendor for something like a USB-UART or some such and any software that may be pre-written as opposed to using hyperterminal/teraterm and developing your own protocol.
It might be better to tell us what you are trying to accomplish. It may be you've got this idea of addressing the FPGA from a PC and it really is a bad way to approach the design.
Indeed, I am using the SEU controller macro to inject SEU into the FPGA. So, firstly, define an address as an injection place, then I would like to readback the content of this address to make sure that the content of address have been changed due to SEU injection. The SEU injection is done via UART and now I am working to readback that address to my PC.
So, by this explanation, can you please let me know what to do?
Regards,
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