How to put IO pads in a layout?

[s3034585]

Hi
Can any one pls tell how to selecte IO pads and how to put them..
I have done block level layout now i need to put IO Pads..I have never used them before. Thus can one tell me the flow once the layout is ready for putting IO pads..
Where can i get information to read on this...
Thanks in advance...
tama

 

[sunking]

How to put IO pads

do you have a floorplan? just flow it first.
the pad should near the layout, analog and digital have difference place and so on.

 

[s3034585]

Re: How to put IO pads

Hi Sunking
I have the floor plan ready... Now i need to put the pads for it.
So can you tell me the complete cycle for it.

Thanks
Tama

 

[xysafety]

Re: How to put IO pads

Then you need define a file for PAD including the position and direction,
In P&R tools, you can call it in, then you can see it ..

 

[sankudey]

Re: How to put IO pads

Do you have analog and digital...both pads required?....generally they are provided...you can find in your kit/library....

if not...for analog some times only metal pad does work...but the detailed know-how you can find in literature.....the digital pad should be provided.....

if you have only digital pads....then they need to put in a ring form encircling ur core circuit....the circlr should not have any discontinuity...for this some corner pads also provided there....the continuous nature basically distribute the vdd/gnd etc required to drive the internal circuits of the pads and also for the esd protection circuits out there....

 

[yankuangtu]

Re: How to put IO pads

In the prototype system design,can i just open a window for I/O connect and without ESD for output signal in order to output the signal at high frequency?

 

[mady79]

Re: How to put IO pads

check the pads driving capability,Fanin ,Fanout and delays
Use multiple pads for vss and possible for vdd as well .

 

[yankuangtu]

Re: How to put IO pads

For high frenquency output,such as pll's output,can we use a PAD without the big capacitive load-ESD?How usually people design a PAD for RF purpose?

 

[s3034585]

Re: How to put IO pads

Hi
Thanks to all of you for ur replies..
after deciding the pad types wht is the next step. I mean that now one has decided the core boundary after that pads types...

Can you pls provide more details on this...
Thanks
tama

 

[Teddy]

Re: How to put IO pads

You have to admit that your question is not very clear. What do you eaxctly ask for?
In general your I/O placement is dictated by a) spec sheet / package pin specification and b) by leadframe ( in general bonding) where you must make sure that I/Os will be connected to leadframe and that the bonding rules are not violated.

Pad size and pad spacing depends on the foundry which performs the bonding (assembly house) - you should get the bonding rules from them. Most of silicon foundries provide pad rules but they really do not care as long as they do not do assembly

For your core - layout of the core should be done with respect of where approximately the bonding pads and I/O structures will be in order to avoid long lines across the die. For DC signals it does not matter that much but for i.e. Clock it would be stupid to have CLK I/O on the bottom of the die and connection to the core on the other (top) side.

Usually it is a good idea to surround the core by a guardring(s) to protect it from the I/O influence.

Connection to the core could be (depends on purpose of the path) minimum metal but the minimum metal should be after all the ESD structures. Before them from Pad to ESD you should use something much wider.

For RF pads quite a few people just decrease the ESD performance in spec.
For the outputs it is usually not a big deal since the output structures are self protective.

For RF( by that I mean fast switching) pads use last metal only to decrease the parasitic capacitance. Routing in last meat to the core is a good idea.


I just hope you have fun

 

[kichu_kavi]

Re: How to put IO pads

The concerns while designing IO pads are the available metal lavel and the type of packaging
and the bonding pitch. If the package is a wire bond one you need to place your pads along the periphary .

 

[yankuangtu]

Re: How to put IO pads

Teddy：
you said that just use last metal.do u mean that in the layout,do not full of the pad with each metal just as usually we do,in order to reduce the capacitive load?
but i wonder that for the PAD the most of the load of it is the ESD circuit,so maybe i have to make the ESD device smaller size.
another question is that if i can accept the low pass characteristic--which means that i can accept the amplitude reduction at the frequency of my output signal then,i can modify the PAD less，am i right?
thank u anyway