How to promote the debugging effency of FPGA??

[zzp6682]

I often use the signal tap or reval to debug my fpga. However I find the effency is a little low with my expactation? For every revision, it needs a lot of time to re-compile the all project and generates the download file. Does anyone give me a good way to debug the complex fpga??

 

[TrickyDicky]

First of all, test each component in isolation in modelsim
Then test the system in modelsim.

Those two steps should reduce debug time on a real FPGA.

 

[lucbra]

I'm not actually sure that it reduces debug time, but at least you keep the overview ...
Probably it takes less time to debug small units, but at the end you need to compile, synthesize, the complete design.

I also recommend to write a good testbench (for all the submodules).

 

[TrickyDicky]

it would do if you were trying to do all of your debugging with signal tap!

 

[lucbra]

Agree, but can you hook your SignalTap module 'on the fly' to other parts of the design or do you need to recompile?

 

[TrickyDicky]

The whole design needs recompiling whenever you change what you're looking at in signal tap. Plus with signaltap (or chipscope) you have to use internal resources, so log size is limited by available internal memory.

 

[lucbra]

Do you see what I mean?

SignalTap will serve it's cause, but a good testbench (Ok you'll need time to write it) can help a lot.
and I've seen strange things when using signaltap : change of routing, worse timing, not meeting time constraints, ...

very unpleasant when it takes more than 24hr to synthesize ...

 

[zzp6682]

OK. Writing one good testbench is a difficult task for one big design. It needs more efforts to acomplish this task for each detail. Is it one way to record all histroy in the actual debugging??