How to produce time delays using VHDL?

[bekirhakan]

using time delay

Hi everybody...

I have a guestion. I want to produce time delay using
VHDL. If the input signal rises '1' from '0' , the output signal
must rise '1' from '0' after 5 seconds. If the input signal
falls '0' from '1' , the output signal must fall '0' from '1' after
5 seconds. How can I produce this time delay ? if you help me,
you will make me happy.

Thanks in advance...

 

[SphinX]

using time delay

Hi man,

use word "after"

Look at

**broken link removed**

Bye

 

[voho]

Re: using time delay

Hi

This entity is a simple inverter with a delay
ENTITY inv IS
PORT (
i1: IN BIT;
o1: OUT BIT
);
END inv;
ARCHITECTURE single_delay OF inv IS
BEGIN
o1 <= NOT i1 AFTER 5 NS;
END single_delay;

 

[voho]

Re: using time delay

Hi

Again example

ENTITY and2 is
GENERIC(trise : delay := 10 ns;
tfall : delay := 8 ns);
PORT(a : IN level;
b : IN level;
c : OUT level);
END and2;


ARCHITECTURE behav OF and2 IS
BEGIN
one : PROCESS (a,b)
BEGIN
IF (a = '1' AND b = '1') THEN
c <= '1' AFTER trise;
ELSIF (a = '0' OR b = '0') THEN
c <= '0' AFTER tfall;
ELSE
c<= 'X' AFTER (trise+tfall)/2;
END IF;
END PROCESS one;

END behav;

 

[bekirhakan]

Re: using time delay

hi all...

I want to use this program for synthesizing
the FPGA. I think, 'after' clause is used only
for simulation. Am I right? And I want to use
time delay 5 seconds or 10 seconds.

bye...

 

[ydao]

using time delay

Right, "after" clause is used only for simulation. So you see, it does not rely on the language how long delay occurs between the ouput signals and inputs. So you must look up for the device's support. Maybe I would use buf or other combinational logic to implement the 5 ns delay. At the end, this is not a good method and the accurate delay will be temperature relative.

 

[moira]

Re: using time delay

after is useless for synthesizing.

i've seen an article abt how to delay.

the high frequency clk will be used to drive a shift register,
the input is the signal u want to delay,
configurating the register according to the delay time of the signal.
the output is the delay signal.

but this method will cause error,so we can resample the signal with data clk.

 

[Al Farouk]

Re: using time delay

Here is what you want, attached is a syntheziable code for a delay element The load is the input signal and done is the output one. change the counter length to get dufferent delays
( Delay = CounterLengthxClok period)