How to prevent Synopsys Design Compiler(DC) treating adder as blackbox

[ammmmlol]

Hi,
I am trying to synthesize an adder like the one in Sparc T1-cpu.
The code contains two 16-bit adders like the following.

   assign      {cout16, adder_out[15:0]} = rs1_data[15:0] + rs2_data[15:0] + 1'b0;
   assign      {cout32, adder_out[31:16]} = rs1_data[31:16] + rs2_data[31:16] + cout16;

And the cell report looks like this.

Cell                      Reference       Library             Area  Attributes
--------------------------------------------------------------------------------
dp_cluster_0/add_1_root_add_39_2
                          DW01_add_17.blackbox.rpl        0.000000  b, d
dp_cluster_0/add_38       DW01_add_17.blackbox.rpl        0.000000  b, d
--------------------------------------------------------------------------------
Total 2 cells                                             0.000000

DC treats DW adder as black box, don't touch and doesn't do any mapping. So I can't get any power or timing information.
I tried to remove one adder, and DC could actually synthesize one 16-bit adder. So I think there is no problem for DC mapping a 16-bit DW adder.

How do I tell DC to actually synthesize my module when I have multiple adders.
Thanks

 

[ThisIsNotSam]

Could this be an issue with DW library linking?

 

[ammmmlol]

I have no clue. This is the tcl script I use for setting up the library

set synthetic_library "dw_foundation.sldb"
set target_library "gscl45nm.db"
set link_library "* $synthetic_library $target_library"

What command should I add that may fix this problem?
Thanks

 

[slutarius]

Have you check whether DesignWare license has been available on your environment ?

 

[ammmmlol]

Have you check whether DesignWare license has been available on your environment ?

This is the output I got from dc when I executed compile command:

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | K-2015.06-DWBB_201506.0 |     *     |
| Licensed DW Building Blocks        | K-2015.06-DWBB_201506.0 |     *     |
============================================================================

So I believe the license is available, or is there any other way to check the license?

 

[slutarius]

I am not sure about license checking. But if you can go through the run without any Error or critical Warning,
it seems license to be OK.

Is there any other Warning say that your combined design has DW component ?
As I remember, there is a warning with a reason for that DW to be existed after compiling by DC.