zswong
Newbie level 2
Hello EDA users,
I am using IC Compiler for layoutting and manually placed stack vias to connect from power rails (Metal1) of standard cells rows to the top-layer power straps (Metal 6). But during routing (route_opt), these manually placed stack-vias are "removed" and the power rails are "floating". The log does not specify any "removal". However,the stack-vias automatically placed by the tool during power-network synthesis remains after routing.
I split the routing procedure into "route_zrt_global" "route_zrt_track" "route_zrt_detail" stage and check for power-ground connection using "verify_pg_net" after each stage and found that after "route_zrt_track", the power-ground connection "floated" because the stack-vias are "removed".
Is there a way to prevent the "removal" of these manually stack-vias during routing?
Any suggestions, comments are welcomed and appreciated.
I am using IC Compiler for layoutting and manually placed stack vias to connect from power rails (Metal1) of standard cells rows to the top-layer power straps (Metal 6). But during routing (route_opt), these manually placed stack-vias are "removed" and the power rails are "floating". The log does not specify any "removal". However,the stack-vias automatically placed by the tool during power-network synthesis remains after routing.
I split the routing procedure into "route_zrt_global" "route_zrt_track" "route_zrt_detail" stage and check for power-ground connection using "verify_pg_net" after each stage and found that after "route_zrt_track", the power-ground connection "floated" because the stack-vias are "removed".
Is there a way to prevent the "removal" of these manually stack-vias during routing?
Any suggestions, comments are welcomed and appreciated.