how to prepare the nelitst with IO pad ?

[owen_li]

Hi.

After we finish the RTL coding for a design, the netlist has no IO pad definition.

So how to implement the IO pad for the boundary of the chip ? Is there any tool

for the implementation?

Thanks!

 

[boilice]

Hi.

After we finish the RTL coding for a design, the netlist has no IO pad definition.

So how to implement the IO pad for the boundary of the chip ? Is there any tool

for the implementation?

Thanks!

yes, I have a same question,thanks.

 

[nsingh95]

Hi.

After we finish the RTL coding for a design, the netlist has no IO pad definition.

So how to implement the IO pad for the boundary of the chip ? Is there any tool

for the implementation?

Thanks!

yes, I have a same question,thanks.

Hi,
You can either search in your directory for padlib file i.e.gives details of your inpad ,outpad logic and compile it.

Even without doing the above things you can synthesize ur design using synopsys DC compiler and generate netlist , You will get some warning.
But if you further use your netlist for DFT purpose you will get lots of black boxes which will effect your coverage.
So, its good if you find the pad lib file.