How to predict the phase noise of PLL?

[answer]

thanks

 

[Y.C Park]

Hello

You can simulation by cadence PSS simulation.
To reduce simulation time, You'd better change digital block to VerilogA models.

Thanks.

 

[lewisflame]

Do we have to consider phase noise of PLL, when we design a pipeline ADC system modeling where clock is generated by PLL?

 

[khouly]

u can predict PLL phase noise simply by hand analysis , but it is hard

1) check if major contributin of the phase noise
2) check the transfer function of the PLL due to this source

note . for phase noise from reffernce "the PLL is low pass filter"
for phase noise from the VCO "the PLL is high pass filter

3) caluate the gain and attenuation of every source , add them finally

this is a crude approximation for phase noise calculation

but if u want a accurate results , PSS with phase noise simulation is a must

khouly

 

[jfyan]

thanks

hi,
i suggest you join anthoer forum:
https://www.designers-guide.org/.
i think it is one of the most technical forum about jitter and phase noise to PLL.
enjoy.
jeff.yan

 

[shaikhsarfraz]

Hi,
You can predict the phase noise of PLL by performing PSS and PNOISE analysis.

Thanks
Shaikh Sarfraz