Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to pre-define the clock period in vhdl coding itself?

Status
Not open for further replies.

deepthi.reddy.912

Newbie level 5
Joined
Apr 19, 2011
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,447
Hi,

Is there any possibility to pre-define the clock period in vhdl coding itself so that the code will be synthesized with that frequency.

I have used the following piece of code but it is showing error.

architecture arch1 of controlckt is

signal Q,Q1,Q2,Q3,Q4 : std_logic := '0';
signal t: std_logic := '1';
--constant clk_period : time := 50 ns; --How to select the clock period correctly
begin
NET clock PERIOD := 5 ns ; -- showing error
process(clk)
begin

The input clock in the circuit is 100ns 50% duty cycle.

I want output clock period that is to be synthesized at 5ns. Is there any means for that?
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,082
Helped
2,078
Reputation
4,173
Reaction score
2,034
Trophy points
1,393
Activity points
39,300
No. Timing constraints have to be added in the appropriate file type depending on your synthesisor.

You can set up clocks in testbenches though, but not synthesis. Clock periods would have no use in synthesis anyway.
 

permute

Advanced Member level 3
Joined
Jul 16, 2010
Messages
923
Helped
295
Reputation
590
Reaction score
268
Trophy points
1,343
Activity points
8,543
This is more similar to how altera and synopsys do things. IMO, it makes more sense. I always have issues with UCF files because a net gets removed or renamed in synthesis and suddenly MAP errors out. When the synthesis tool is able to generate the UCF, it knows what it renamed the net to, or if it removed it. SDC also allows for some TCL scripting.

Clock periods do have a use in synthesis because synthesis does optimizations. Knowing which paths are slow vs fast allows the synthesis tool to make good decisions about area/speed tradeoffs.

But it looks like you want a clock synthesizer -- something like a PLL. These cannot be inferred. I suggest coregen or an instance of the correct PLL/DCM primitive.
 

Alexium

Full Member level 2
Joined
Jan 6, 2011
Messages
148
Helped
39
Reputation
78
Reaction score
39
Trophy points
1,308
Location
Ukraine
Activity points
2,163
Xilinx ISE allows specifying constraints in VHDL file using attributes. I use it for clock signals that are generated inside the module and are not present in the interface.
Is this what you need?

Code:
[syntax=vhdl]attribute period: string;  
signal clk:std_logic:
attribute period of clk : signal is “20 ns”;[/syntax]
 
Last edited:

deepthi.reddy.912

Newbie level 5
Joined
Apr 19, 2011
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,447
I am using wave-pipelining on FIR Filter. Usually in non-pipelining and pipelining only maximum combinational path delay is considered. I got this from Xilinx synthesizer and timing anlyzer as 10.836ns.

But in wave-pipelining, we consider (minimum clock period>= (max path delay -min path delay)+uncertainity);
I got this as 5ns;

How can i use this as a input from vhdl coding to set the minimum clock period for oeration of the circuit?

I hope i am clear. Kindly help.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top