deepthi.reddy.912
Newbie level 5
Hi,
Is there any possibility to pre-define the clock period in vhdl coding itself so that the code will be synthesized with that frequency.
I have used the following piece of code but it is showing error.
architecture arch1 of controlckt is
signal Q,Q1,Q2,Q3,Q4 : std_logic := '0';
signal t: std_logic := '1';
--constant clk_period : time := 50 ns; --How to select the clock period correctly
begin
NET clock PERIOD := 5 ns ; -- showing error
process(clk)
begin
The input clock in the circuit is 100ns 50% duty cycle.
I want output clock period that is to be synthesized at 5ns. Is there any means for that?
Is there any possibility to pre-define the clock period in vhdl coding itself so that the code will be synthesized with that frequency.
I have used the following piece of code but it is showing error.
architecture arch1 of controlckt is
signal Q,Q1,Q2,Q3,Q4 : std_logic := '0';
signal t: std_logic := '1';
--constant clk_period : time := 50 ns; --How to select the clock period correctly
begin
NET clock PERIOD := 5 ns ; -- showing error
process(clk)
begin
The input clock in the circuit is 100ns 50% duty cycle.
I want output clock period that is to be synthesized at 5ns. Is there any means for that?