how to perform division by three in xilinx

[mansi0905]

i need to perform division in vhdl in ise environment by other than powers of two. i need to do this in single clock cycle. i facing this problem since ise environment does not support division by other than powers of 2

pls help
thanx in advance

 

[yoramgr]

How many bits? Maybe you can prepare a look-up table in ROM.

 

[mansi0905]

the operation is being performed in integer so i guess 32 bits.
how can i use look-up table in ROM for division pls elaborate

 

[lostinxlation]

the operation is being performed in integer so i guess 32 bits.
how can i use look-up table in ROM for division pls elaborate

I'll give you a hint and you'll figure out the rest.

A random number up to 999, divided by 3
Suppose you divide 245 by 3.
245/3 = (200 + 40 + 5)/3

Have a table that produces the quotient and remainder for dividend, 100, 200, 300... 900.
Have another table for dividend, 10, 20, 30, ... 90 to do the same.
Have one more table for dividend, 1, 2, 3, ...9. to do the same.

A little manipulation required between the ROM accesses and you need to consider some corner cases.

 

[yoramgr]

More details about look-up table in ROM: ROM is a memory device with constant numbers stored in it. It has an address input bus and a data output bus.

Example of ROM with look-up table for dividing numbers 0 to 7:


Address Data
------- ----
0 . . . 0
1 . . . 0
2 . . . 1
3 . . . 1
4 . . . 1
5 . . . 2
6 . . . 2
7 . . . 2


The above is good enough for a 3 bit integer. Connect the number you want to divide by 3 to the address bus, and get the result from the data bus (rounded to the nearest integer).

If your data path is 8 bit, it is still practical to use a single look-up table ROM: the ROM size would be 256 bytes. For 32 bit it not practical to use a single ROM, so you'll have to split the number, as suggested by lostinxlation.

 

[Teg-Men]

How about other numbers, ex. I want to divide 90 by 8. If I use "for" statement to subtract 8 from 90 n times -until negative numbers- how much time do I need. If our fpga's clock is 25 MHz. and we get incoming signal that is 25 Mhz too, and start to count it, then does my result come after 1 sec?