how to pass more than one parameters in verilog

[bapodradhairyab]

I want to know how we can pass parameters through the top module to the instance inside the top module and what is exact syntax for that...

 

[devas]

Hi,

Verilog-95 style in the parameter order as defined in the lower level module:

<submodule name> #(<value1>, <value2>, ..., <valueN>) <instance name> (<port connections>)

Verilog-2001 style uses named assignments:

<submodule name> #(.<param1>(<value1>), .<param2>(<value2>),..., .<paramN>(<valueN>)) <instance name> (<port connections>)

Devas