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How to pass LVS of a MOM capacitor

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hrivandi

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Dear all,

I want to implement a MOM capacitor in TSMC 180nm technology. in this regard, a schematic including two inutoutput pins, and a corresponding symbol are created. After that, the layout of a 40um*40um MOM capacitor is implemented. The DRC is clean, however, I cannot pass LVS (I am using nmLVS, calibre), saying there is nothing in source and layout.
1615730947354.png

I tried to solve the problem with LVS BOX, as you can see here, but nothing changed. Does anybody have a solution for it?
1615731079577.png
 

there are 2 steps i could think about.

1st step, you should check if you've applied any filter on source and layout for mom, if yes, you should remove them
2nd step, you could check the .sp file (for layout netlist) and schematic netlist file, if there is the momcap type of your design there. In your snapshot, it's possible that the momcap subckt isn't there, you should contact the one who provides you pdk for this issue.

hope this help.
 

If by "implement" you mean draw your own
polygon stack, there's more to extraction than
just the printable layers.

Is there no MOM cap in the PDK device set?

If there was, you'd look at it to see what other
objects may be included - like a "capacitor"
recognition layer, similar to how poly can be
made to be extracted as a resistor instead
of local interconnect by saying so.

You could read the extraction rules deck and
see whether there is -any- MOM cap logic. If
so then read some more to see what it entails,
and add what it's looking for.
 

Hi,

There's one simple solution.
This issue is because of mom is not recognizing as device, so keep one lvs resistor(metal resistor) at input or output side of cap. Then it will compares lvs.
 

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