hrivandi
Newbie
Dear all,
I want to implement a MOM capacitor in TSMC 180nm technology. in this regard, a schematic including two inutoutput pins, and a corresponding symbol are created. After that, the layout of a 40um*40um MOM capacitor is implemented. The DRC is clean, however, I cannot pass LVS (I am using nmLVS, calibre), saying there is nothing in source and layout.
I tried to solve the problem with LVS BOX, as you can see here, but nothing changed. Does anybody have a solution for it?
I want to implement a MOM capacitor in TSMC 180nm technology. in this regard, a schematic including two inutoutput pins, and a corresponding symbol are created. After that, the layout of a 40um*40um MOM capacitor is implemented. The DRC is clean, however, I cannot pass LVS (I am using nmLVS, calibre), saying there is nothing in source and layout.
I tried to solve the problem with LVS BOX, as you can see here, but nothing changed. Does anybody have a solution for it?