Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to pass data b/w Synchronous Domains

Status
Not open for further replies.

spartanthewarrior

Full Member level 2
Joined
Jun 13, 2007
Messages
122
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,142
Hi All,

Can any body tell me

How to pass data between two synchronous domains?

Regards
 

Synchronous domains need to be balanced during CTS. If one frequency is a multiple of another, then the design must ensure the faster domain does not sent data faster than the slower domain can handle.
 

people use dual rank synchronizers to pass data. i.e. chain of two flip flops .
 

Hi,

Two flop synchronizer works well if you are sending data form slower clock domain to faster clock domain. In reverse way some data may lost.

so to transfer data from and to either domain handshake synchronization is must.

--
Shitansh Vaghela
 

If it's synchronous and the same frequency, then you don't need to do anything. If it's synchronous but the frequencies are multiple of each other, then you need to stretch the fast clock's signals to match the slow clock's frequency or else you might not be able to latch it correctly.

Some of the responses are for data transfer across an ASYNCHRONOUS clock domains, so you can ignore them.

- Hung
 

Sample the data with the negedge of high sync clk and
use it with the low sync clk

Data rate should be compatible with low sync clk.
 

skyfaye said:
If it's synchronous and the same frequency, then you don't need to do anything.

It's important to ensure that data is not sampled on or near clock edges where it might change. If two domains have clocks that are "almost" perfectly in sync, you should have data leaving each domain change on the opposite clock edge from where it will be sampled in the other. To minimize "round trip" lag, it may be helpful to, if you can, have the two domains operate on opposite clock edges from each other. That way, the delay when passing between domains would be a half clock rather than a full clock.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top