abselgec
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Hi,
I have the following system verilog code to be compiled in VCS.
module (....);
.....
......
parameter WIDTH = 8;
parameter [2:0][WIDTH-1 : 0 ] = {8'h00, 8'hff, 8'h24} ;
....
..
endmodule
How can i parameterise the size of literals inside the concatenation? so that even if WIDTH changes i need not bother about changing the size manually inside the concatenation.
I know this may work for all 0's and 1's by using 'h00, or '1. (although former gives vcs warning since unsized literals are taken as 32bits). But i have no idea how to use it with something like 8'h24. Please help on this at the earliest.
Thanks & Regards,
Absel.
I have the following system verilog code to be compiled in VCS.
module (....);
.....
......
parameter WIDTH = 8;
parameter [2:0][WIDTH-1 : 0 ] = {8'h00, 8'hff, 8'h24} ;
....
..
endmodule
How can i parameterise the size of literals inside the concatenation? so that even if WIDTH changes i need not bother about changing the size manually inside the concatenation.
I know this may work for all 0's and 1's by using 'h00, or '1. (although former gives vcs warning since unsized literals are taken as 32bits). But i have no idea how to use it with something like 8'h24. Please help on this at the earliest.
Thanks & Regards,
Absel.