I don't want to change RTL code more and want to add some constraint to output design internal signal to FPGA IO.
Who can give me some guideline?
I remember xillinx device can support such feature with constraint.
ISE FPGA Editor has a probe feature that allows you to open a placed and routed design and designate that a net in the design is routed to a pin.
Vivado allows you to take a synthesized design and designate pins a debug probes, which can be connected to an ILA/VIO. The ILA/VIO and control are inserted when you place and route the design. I don't recall seeing anything about routing an internal net to a pin, without adding it to the HDL code.