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How to multiply two numbers in VHDL?

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iliya24

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Hello.
I am anew to vhdl please help me i need to multiply 2 numbers like we did in high scool.

I have write a code that logically is seems to be ok and also is compiling but the answer not good.
Thx

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

ENTITY Fullheader IS PORT(
A,B: IN unsigned (3 downto 0);



y : OUT unsigned (7 downto 0));


END Fullheader ;
ARCHITECTURE Behavioral OF Fullheader IS

BEGIN

process (A,B)
variable temp:unsigned(7 downto 0) ;
variable temp1:unsigned(7 downto 0);
BEGIN



for j in 0 to 3 loop


temp1:=( j=>a(0),j+1=>a(1), j+2=>a(2),j+3=>b(3),others=>'0') ;
temp:=temp1+temp;

end loop;

y<=temp;





end process;
END Behavioral;
 
Last edited:

TrickyDicky

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Re: multiply two numbers

Whats wrong with:

Y <= A*B;

---------- Post added at 22:22 ---------- Previous post was at 22:21 ----------

Whats wrong with:

Y <= A*B;
 

iliya24

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Re: multiply two numbers

There is no problem with what u offered but i need it in old fashion way because this is the task i need to solve.
Thx
 

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