How to move gate level netlist to FPGA verification?

[harryzhu]

I've finished to synthesize and get netlist, but I modified something to it, so I run formality to do formal verification, after that I need to do FPGA verification to the gate level netlist, but how should I transfer it?

I read the netlist directly to Quartus, finished the whole flow and burn into FPGA. These step seems like including no timing info, so it have no more meaning.

I don't know if there's some tools to do it, such as FPGA compiler or others. If you have such experience, would you like to help me or give some advice? Thanks for your help

Have a good day!

Best Regards,

Harryzhu

 

[anjali]

netlist can be ported into FPGA, using JTAG interface or burning the EPROM, through which FPGA get programmed. for that,

bitgen file has to be converted into PROM format (MCS,EXORMAX,TEKHEX). we can use PROMgen of ISE. so generate PROM file, and download into EPROM. (from that FPGA will be programmed)

Added after 1 minutes:

netlist can be ported into FPGA, using JTAG interface or burning the EPROM, through which FPGA get programmed. for that,

bitgen file has to be converted into PROM format (MCS,EXORMAX,TEKHEX). we can use PROMgen of ISE. so generate PROM file, and download into EPROM. (from that FPGA will be programmed)

 

[gliss]

You probably want to check the new netlist against the original HDL in something like Synopsys Formality. You don't need timing because you are verifying function, not implementation.

 

[harryzhu]

But I haven't do more work on verification, I just add some test point on function simulation, so I'm not sure if it has bugs.

 

[gliss]

Apply the same test vectors on the new netlist. That should give you an idea of functionality.

 

[harryzhu]

Well, maybe I should tell you my real idea. We have one chip with bugs, so we have to debug it. But since we've done poor testbench and verification, after we modified the gate level netlist, we run formal verification with formality, and at the same time we read the netlist into quartus to run FPGA verification. Our boss is a opinionated person and he think we cannot ensure the right of RTL function since the missing testbench and ask us to read the ASIC's timing info into FPGA to verify the timing, but as me know, FPGA verification can only test the function but not timing and FPGA's timing is different completely with ASIC, even we read into ASIC's timing info, there'll be no more help to the timing verification.
Now I'm searching one tool to do the transfer until I find DC FPGA, I've not used the tool and am not sure if it can do it. Who have used them and give me more help?

Have a good day and thanks for your help!

Best Regards,

Harryzhu