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How to model the switched-capacitor Half Cycle Gain Stage

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ynhe

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google capacitor in s domain

How to model the switched-capacitor Half Cycle Gain Stage (with offset compensation)using a four-port, z-domain equivalent model?


Thanks!
 

I could not understand your question. Please explain your problem more. You can also read the Switch-Capacitor Chapter of the book "design of analog CMOS integrated circuits" written by Razavi. He explained everything clearly in that book.
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

i din't get ur question right yet, but i have a couple of questions... first, assuming u give a ac input, i don't understand still becoz, the capacitor will block that... but then leaving that, the feedback capacitor gets charged during the positive half cycle and then if u close the circuit, then by basic laws of electrical theory, the capacitor cannot get discharged instantaneously... and second, if it is dc, then i have studied in sedra and smith that there will be many problems with regard to stability, but nevertheless, we use a resistor resulting in the circuit behaving as a non-ideal integrator or differentiator(not in the circuit u have shown, but usually with the feedback capacitor...)

anyway, could u expolain this question clearly with not much technical terms...

regards,
Arun.
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

I am far from expert in switched-capacitor circuits, but it seems to me that you can't model this circuit using a Z-domain model, even
though it is a sampled system due to the switched-caps. The input signal
and the op-amp are continuous time so you have to model the whole
thing using laplace (s) domain rather than the z domain. Basically, what
I would do is figure out the equivalent continous time behaviour of the
switched caps for the particular frequency you will be switching them at,
then find laplace domain expressions for them, and finally come up with
a model for the entire circuit.
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

Hi,all
Although the switched capacitor circuits considered so far can be analyzed with reasonable effort manually, more complex switched capacitor circuits will become a challenge. To provide a way to meet this challenge and to confirm the hand analysis results, Some scholars developed
z-domain models of switched capacitor circuits. These models
will allow us to both analyze more complex switched capacitor circuits and to perform frequency domain simulation using SPICE-type simulators.
Follows are some four-port, z-domain equivalent models.
More detail on the model development can be found in K.R. Laker, “Equivalent Circuits for Analysis and Synthesis of Switched Capacitor Networks,” Bell System Technical Journal, vol. 58, no. 3, March 1979, pp. 729-769.
If somebody have this paper,please share with us.
My question is how to model the switched-capacitor Half Cycle Gain Stag using these standard SC z-domain model blocks.I am tring,hope somebody give some suggestings.

Thanks!

ynhe
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

Hi,all
Is it possible to accurately model the FPAA's Half Cycle
Gain Stage (with offset compensation)using some four-port, z-domain
equivalent model?
Do you have some new ideals?

YNHE
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

The answer to your question is in chapter 10 of Analog Integrated Circuit Design by Johns & Martin.

YOu must calculate the charge in every node at each clock cycle in function of the value in the previous clock cycle.

The call the charge at the present clock cycle Q(z), so the charge at the previous cycle would be Q(z)/z. Solving for Vout as a functions of Vin, you'll get the discrete transfer function.
 

Re: How to model the switched-capacitor Half Cycle Gain Stag

This is my result I tried.I simulated it with SPICE successfully(gain=1,c1=255pF,c2=255pF,Vos of OPA is 2mV).
If OPA is considered as ideal,this model can be simplified more as a transfer
function.H(Z)=(c1/c2)*z^1/2

ynhe
 

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