How to model Pad, Bond-wire and channel behavior in design

[circuitking]

Hello,

I have an ASIC that is sending data to FPGA.

Between ASIC and FPGA, I would have LVDS (including Pre-emphasis), Pad, bond-wire, and channel. do all kinds of FPGA's LVDS pins have input impedance as 100 ohm?

Now, I want to estimate the behavior of the Pad, bond-wire, and channel and include them in the LVDS design.

Anyone has inputs on this?. Thanks

 

[dick_freebird]

1nH/mm of bond wire. Coupling, you'd need
a good EM simulation package. You can get
bond wire resistance from wire vendors or
third party assembly houses' web pages,
need to know wire diameter and material
(or whether wire-bonded at all; bumps /
pillars are a whole 'nother thing).

Bond pad you could estimate as areal C of
Met1 over field, dimensions from layout,
thicknesses from PDK modeling / device
construction docs (though what's provided
or even allowed to be seen, varies by foundry).

LVDS pins will have 100 ohms between them
but you can't assume this is all. There will be
ESD protection, which presents C and at some
point, conduction to the rails.

You might cheat and look for other LVDS ASIC
pads' IBIS models etc.

 

[circuitking]

Bond pad you could estimate as areal C of
Met1 over field,

What do you mean by Metal1 over field?

 

[dick_freebird]

Pads will not be over active area (unless a specific
enablement of circuit-under-pad is made in the
PDK). You ought to see the full un-cut field oxide
thickness between lowest metal of the pad-stack,
and the silicon surface.

There is probably, somewhere in the PDK RCX "stuff",
area and periphery capacitance numbers for Met1
not-over-active.