// VerilogA for Test, Transponder_Signals, veriloga
`include "constants.vams"
`include "disciplines.vams"
`define Nums_of_Plucking 8
module Transponder_Signals(induced_current_p, induced_current_n, fdevsw, lfmodin);
inout induced_current_p, induced_current_n;
output fdevsw, lfmodin;
electrical induced_current_p, induced_current_n;
voltage fdevsw, lfmodin;
parameter real fc=134.2k from (0:inf);
parameter real Ac=80u from (0:inf);
parameter real duration=150m from [0:inf);
parameter real logic_high_level=6.0 from (0:inf);
parameter real Tlow_for_fdevsw=118.8u;
parameter real Thigh_for_fdevsw=129.3u;
parameter real Tdelay_for_fdevsw=duration + 300u;
parameter real Trise_for_fdevsw=Tlow_for_fdevsw/1000;
parameter real Tfall_for_fdevsw=Tlow_for_fdevsw/1000;
parameter real fres_for_low=134.2k;
parameter real fres_for_high=125k;
parameter real Tdelay_for_low=0.0;
parameter real Tdelay_for_high=0.0;
parameter real Twidth_for_low=(1/fres_for_low)/4;
parameter real Twidth_for_high=(1/fres_for_high)/4;
parameter real Trise_for_low=Twidth_for_low/100;
parameter real Trise_for_high=Twidth_for_high/100;
parameter real Tfall_for_low=Twidth_for_low/100;
parameter real Tfall_for_high=Twidth_for_high/100;
parameter real period_of_plucking_for_low=Tlow_for_fdevsw/`Nums_of_Plucking from (0:inf);
parameter real period_of_plucking_for_high=Thigh_for_fdevsw/`Nums_of_Plucking from (0:inf);
real logic_low_level;
real vout_val_for_fdevsw;
real turn_off_for_high[1:`Nums_of_Plucking];
real turn_off_for_low[1:`Nums_of_Plucking];
real vout_val_for_high[1:`Nums_of_Plucking];
real vout_val_for_low[1:`Nums_of_Plucking];
real time1, time2, local_time;
genvar i;
voltage fdevsw_int, lfmodin_int;
real aho1, aho2;
integer iflag1, iflag2;
integer my_edge;
analog begin
$bound_step((1/fc)/16.0);
@(initial_step) begin
my_edge = -1;
iflag1 = 0;
iflag2 = 0;
time1 = -1G;
time2 = -1G;
logic_low_level = 0.0;
vout_val_for_fdevsw = logic_low_level;
for(i=1; i<=`Nums_of_Plucking; i=i+1) begin
vout_val_for_high[i] = logic_low_level;
turn_off_for_high[i] = -1M;
vout_val_for_low[i] = logic_low_level;
turn_off_for_low[i] = -1M;
end
end // initial_step
if($abstime <= duration) begin
I(induced_current_p, induced_current_n) <+ -Ac*sin(2*`M_PI*fc*$abstime);
end
else begin
I(induced_current_p, induced_current_n) <+ 0.0;
end
@(timer(Tlow_for_fdevsw, Tlow_for_fdevsw+Thigh_for_fdevsw)) begin
vout_val_for_fdevsw = logic_high_level;
end
@(timer(Tlow_for_fdevsw+Thigh_for_fdevsw+Trise_for_fdevsw, Tlow_for_fdevsw+Thigh_for_fdevsw)) begin
vout_val_for_fdevsw = logic_low_level;
end
V(fdevsw) <+ transition(vout_val_for_fdevsw, Tdelay_for_fdevsw, Trise_for_fdevsw, Tfall_for_fdevsw);
@(cross(V(fdevsw)-logic_high_level/2, +1)) time1 = $abstime;
@(cross(V(fdevsw)-logic_high_level/2, -1)) time2 = $abstime;
for(i=1; i<=`Nums_of_Plucking; i=i+1) begin
/*
if($abstime < duration) begin
vout_val_for_high[i] = logic_low_level;
turn_off_for_high[i] = -1M;
vout_val_for_low[i] = logic_low_level;
turn_off_for_low[i] = -1M;
end
else begin
*/
local_time = time1 + (i-1)*period_of_plucking_for_high;
@(timer(local_time)) iflag1 = 1;
@(cross(V(induced_current_p, induced_current_n), my_edge)) begin
if(iflag1 == 1) begin
vout_val_for_high[i] = logic_high_level;
aho1 = $abstime;
iflag1 = 0;
end
end
turn_off_for_high[i] = aho1 + Twidth_for_high + Trise_for_high;
@(timer(turn_off_for_high[i])) vout_val_for_high[i] = logic_low_level;
local_time = time2 + (i-1)*period_of_plucking_for_low;
@(timer(local_time)) iflag2 = 1;
@(cross(V(induced_current_p, induced_current_n), my_edge)) begin
if(iflag2 == 1) begin
vout_val_for_low[i] = logic_high_level;
aho2 = $abstime;
iflag2 = 0;
end
end
turn_off_for_low[i] = aho2 + Twidth_for_low + Trise_for_low;
@(timer(turn_off_for_low[i])) vout_val_for_low[i] = logic_low_level;
//end
V(lfmodin) <+ transition(vout_val_for_high[i], Tdelay_for_high,
Trise_for_high, Tfall_for_high)
+ transition(vout_val_for_low[i], Tdelay_for_low,
Trise_for_low, Tfall_for_low);
end
end // analog begin
endmodule