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how to model a LDO output current load in simulation

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xiaofeixia

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My LDO is used to support a 1.2V output and 100mA current for digital circuit

when i simulate a LDO, I use a current source witch draw a 100mA current to model output current, but in line regulation simulation, the voltage is minus when the input is small.

but when i use a variable resister witch have a resistance of 1.2/iload, the AC simulation shows a wrong Gain for the resister is much small than the output resistance of the PMOS, but in fact it should be much larger than it.

so how to model the output resistence as the current load of a LDO, thanks a lot
 

u are wrong. The output resistance of Pmos is very large,because you see form drain. The common loads are often resistive, so the second way is right.
 

to smilelangjun:

thanks
yes, but when the load circuit is digital circuit, it operate in switching mode so it's high impedance。

for example, if the digital circuit is composed of inverters, only nmos or pmos is operating and another is shutoff, so seen from the digital power supply, it's high impedance
 

hi xiaofeixia,
please i want to know if your LDO output changes after you use it with your digital?because i have almost the same application of LDO and when i simulate the LDO with digital i have a variation of my Vreg
thanks
 

hi,xiaofeixia

can you give me some advices about Ac simulation about dc-dc converter? such as loop gain and phase, i donot know how to ..
thanks
 

Hi,xiaofeixia
I simulate in this way:use some big inverters(large W/L)put them in parallel,make the input voltage of these inverters be a pulse.
 

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