how to minimize the clock period

[mo.khairy.mo]

Hi all,
i'm writing a vhdl code of ALU on xilinx sparatn-6 XC6SLX45T i constrained the clock to be 2ns (500 MHZ) but when i synthesis the design using XST it's timing summary says that

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.784ns (Maximum Frequency: 84.859MHz)
   Minimum input arrival time before clock: 6.314ns
   Maximum output required time after clock: 3.703ns
   Maximum combinational path delay: No path found

when i implement the design the tool can't map the design due to the following error

At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
   constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
   (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
   alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
   environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.

could anyone please help me to fix this error
BTW i need to run the design on the minimum clock period as much as possible

thanks in advance

 

[AdvaRes]

Hi all,
i'm writing a vhdl code of ALU on xilinx sparatn-6 XC6SLX45T i constrained the clock to be 5ns (500 MHZ)

How That ?
If you wanna a 500MHz clock the period must be 2ns.

 

[mo.khairy.mo]

sorry for this misprint i need it to be 2ns 500mhz

 

[AdvaRes]

Try to simplify your code.
Actually this may be due to delay in the datapaths, input/output delay etc.

 

[vipinlal]

You can post your ALU code here.
The reason that your code works at a very less frequency may be because of multiplication or division operations in the ALU.So try to optimize these operations and you will see a increase in the operating frequency.

For example you can increase the speed of multiplication by using the below method:
https://www.vedicmaths.org/introduction/tutorial/tutorial.asp#tutorial5
But remember that these methods will use more resources(logic gates) in your FPGA.

--vipin
https://vhdlguru.blogspot.com/