How to minimise VCD file size for gate-level sim?

[sjalloq]

Hi there,

I've been struggling with bringing up a power analysis flow for the last week and wanted to get some advice.

We're using VHDL RTL and ModelSim along with Design Compiler and Power Compiler.

In order to generate a backward SAIF file I am having to create a gate-level Verilog netlist because ModelSim doesn't support capturing VCD data on 2d arrays. So far I have tried two flows: one, using the Synopsys PLI with ModelSim to generate the SAIF directly and two, generating a VCD file and converting it to SAIF using vcd2saif.

Using the Synopsys PLI seemed to be very slow. A small block level netlist simulation took over 6 hours. Although it worked, using this flow on larger blocks and chip level isn't attractive.

Switching to the VCD flow to see if it was faster resulted in a huge VCD file being generated and I killed the sim. I was saving to a gzipped VCD outptus file and when I killed the sim it was already over 13GB. Note that this is a small block.

Question:

what is the correct flow for generating a VCD file from a gate-level simulation? If I capture all net toggling then am I capturing unnecessary internal library cell information that is not needed by Power Compiler that is bloating my VCD? I tried using the -nodebug switch to vlog but this prevented capture of 95% of my sequential cells.

Thanks for your help.

Added after 4 hours 16 minutes:

OK, I found my problem. User error as normal. I was using the -nodebug switch when compiling both my library and my netlist.

For those searching in future, the flow should be:

vlib library
vlog -work library -nodebug my_cell_lib/*.v my_mem_cells.v
vlog my_netlist.v
vlog my_tb.v
vsim -L library work.my_tb

And as an example of runtime, logging VCD took 2 hours while using the Synopsys PLI took 6.

Thanks.

 

[win3y]

Hi sjalloq;

I think that dumpping vcd or saif by Nc verilog (Synopsys PLI) will take less time than your current way.
Could you tell me the relation between the result of power estimated and amount of running time is? The result of power is increased directly proportional to amount of running time or not?
Thank you

Win3Y

 

[sjalloq]

Hi there,

unfortunately I don't have access to NC-Verilog, we're a Mentor house.

As for the rest of your question I'm not sure I understand. Do you mean how does the accuracy of the power estimation vary with respect to the total running time of the simulation that generates the VCD? It shouldn't matter as long as your stimulus is an accurate representation of your real world operation.

Thanks.