Measure the voltage difference on a low I/O pin in relation to the GND plane. If you are using a CPLD/FPGA then drive one of the I/Os low, make as many I/Os as possible go from low-to-high and measure the bounce on the I/O pin driven low. Due to inductance in the package leads you'll end up with a higher GND potential inside than chip than on the board. BGAs have lower inductance so lower GND bounce.