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How to measure a voltage beneath an IC package?

jjzn

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I am just brainstorming something beyond my course project ....

There are a few ICs supplied by LDOs on a PCB.
ICs are in LGA, BGA, or other package types alike.
When the IC is running in its active mode, how do you monitor the voltage waveform at a particular load pin beneath the IC package?

This is not difficult to do in my course project, because my course design is as simple as DIP or QFN, where load pins are exposed.
I am just thinking beyond this ....
Appreciate your comments.
 
Hi,

* testing on vias .. or where the according signal trace is accessable
* installing test points during PCB design
* using boundary scan tests

Klaus
 
Thank you Klaus for introducing boundary scan. I have never heard of such techniques but just looked at some documents.

Questions are:
(1) As long as there is a JTAG interface in an IC datasheet, the IC should have the boundary scan cells. Is this true?

(2) How accurate is the voltage read back from the boundary scan chain?
I am thinking about this question mainly from the power delivery, power integrity, noise coupling, etc., on a PCB.​
If the boundary scan is used for checking wired connectivity, it should read back just 0 or 1 logic.​
It won't be able to capture the transient voltage on a pin. Is this correct or not?​
Thanks.
 
Hi,

1) --> read the according datasheet
2) --> read the according datasheet
since there is no general rule

Klaus
 
Boundary scan is generally digital. But adding a test mux can be a good idea esp. during early iterations or if "guts" are complex. The loadings and leakages such things impose have to be addressed.
 
Boundary scan is generally digital. But adding a test mux can be a good idea esp. during early iterations or if "guts" are complex. The loadings and leakages such things impose have to be addressed.
The boundary scan interface is digital.... but still - depending on device - you can read out the results of ADConversions.

Klaus
 
The boundary scan interface is digital.... but still - depending on device - you can read out the results of ADConversions.

Klaus

Could you point me to a sample part number of ADC that has boundary scan?
I randomly looked at a few TI ADC parts, but couldn't find boundary scan in their datasheets.

When you say "read out the results of ADC", do you mean the analog side?
--- Updated ---

Boundary scan is generally digital. But adding a test mux can be a good idea esp. during early iterations or if "guts" are complex. The loadings and leakages such things impose have to be addressed.

The "test mux" is inside the IC, right?
Then, what is a typical circuitry for such a test mux? I wonder how accurate it is.
 
Last edited:
Could you point me to a sample part number of ADC that has boundary scan?
No, I don´t think usual ADCs can do this.
I´ve heard from complex 1000+ pins telcom chips, that can do so.
They are mixed signal chips including ADCs .. and they can perform ADC conversions ...and read out the result.

When you say "read out the results of ADC", do you mean the analog side?
What are the options you see?
I mean: "read out the result of ADC" is rather clear - in my eyes.

Klaus
 
If redundancy/reliability is primary concern there are approaches used in space
and medical applications. A very broad topic in both approaches, solutions.

I have seen dual processors used in medical injection pumps, the processors
checking on consistency between them.

Some solutions using multicore, but same die approaches have obvious limitations.

Solutions that include processors with traps, memory error detection/correction.....

Quite a few papers published by IEEE on these topics.


Regards, Dana.
 

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