how to match in MOS current mirrors?

[longstar]

design cmos current mirror

I want to design a MOS current mirror,but I don't know how to match in MOS current mirrors?Who can give me some idears?Thanks.
Rgds.
longstar

 

[pthoppay]

cmos current mirror

Usually when you want to have good matching in current mirrors, you should not work with minimum length devices, as with minimum length devices % error of mismatch will be more.

Also, do not operate your current mirror in weak inversion as it is very hard to match. (Typical application is for low power circuits, but if you are for high speed you can ignore this point, as you will work only in strong inversion).

Prakash.

 

[Chethan]

mos current mirror

1) Have a large W/L for better matching.
2)Usually there will be some error in the current values in a single stage current mirror bcoz of channel length modulation, hence u can use a cascode arrangement.

 

[chen_Analog]

current matching large ratio

you'd better careful in layout. ususally the mismatch of Vth will be dominate in current mirror.

 

[holddreams]

You can refer Gray's book, page329 to 332------Matching consideration in current mirrors.

voltage routing and current routing.

 

[sunking]

refer to the book:
the art of analog layout

 

[ambreesh]

Hi Longstar,

What type of current mirror are you using.?
Are you looking from design or layout perspective or both?
What supplies are you designing with?

 

[longstar]

thanks,everyone.
I got it.
Firstly,the matching is improved by increasing the gate areas of the transistors.
Secondly,the layout is also important.
longstar

 

[beckchm]

but if you design the circuit , whether you must take the layout into account.

 

[beckchm]

layout is important

be careful of that effect

 

[smilelangjun]

1) Have a large W/L for better matching.
2)Usually there will be some error in the current values in a single stage current mirror bcoz of channel length modulation, hence u can use a cascode arrangement.

I think make sure the area of mos big enough, and decrease the W/L,that can make the vdsat big enough

 

[supreet_95]

First make the size of mirroring transistor(diode connected) such that there is overdrive of 100mV and if the mirroring is a large scale then u can have larger m factor and in layout use interdigitation or commoncentroid. If the mirroring ratio is small then use m factor for diode connected transistor itself and use the above method in layout.
Hope this helps.